The present invention relates to integrated circuits and semiconductor device fabrication and, more specifically, to structures for a skip via and methods of forming a skip via in an interconnect structure.
An interconnect structure may be formed by back-end-of-line (BEOL) processing and used to provide electrical connections with device structures fabricated on a substrate by front-end-of-line (FEOL) processing. Typical constructions for a BEOL interconnect structure include multiple metallization levels arranged in a stack. The metallization levels of the BEOL interconnect structure may be formed by layer deposition, lithography, etching, and polishing techniques characteristic of damascene processes. For example, a dual damascene process etches via openings and trenches in one or more dielectric layers and simultaneously fills the via openings and trenches with conductor to create a metallization level.
Skip vias extend vertically through a metallization level of the BEOL interconnect structure to provide a vertical connection between metallization levels that are separated in the stack by an intervening metallization level. Skip vias may provide area efficiency because skipping the intervening metallization level obviates the need for connecting metallization in the intervening metallization level. However, the via opening in which a skip via is formed has a high aspect ratio because of the need to extend through multiple materials in the stack. The high aspect ratio complicates the etching and filling required to form a skip via.
Improved structures for a skip via and methods of forming a skip via in an interconnect structure are needed.